As is well known by those skilled in the art, a continuing goal in manufacturing and production of memory devices is increased storage in the minimum area or least amount of silicon. This relentless demand for reduction in size has resulted in various new approaches for building memories. Further, although DRAM or volatile type memories are suitable for many uses, the continuous need for refreshing of this type of memory is simply unacceptable for other uses. There are, of course, non-volatile mass storage memories such as magnetic hard drives, but such devices are much too slow for high-speed computer operations. Thus, high-speed non-volatile memories are in greater and greater demand.
For example, flash memory was developed in 1988 and is programmable, erasable and non-volatile. The basic flash memory cell is an NMOS transistor that has been modified with a “floating” gate. The flash memory cell is programmed by applying a high voltage to the transistor gate or the WL (word line). If a “zero” bit is to be programmed, a high voltage is also applied to the drain by way of the BL (bit line). These voltages excite the electrons such that they push through the thin oxide layer and are trapped on the floating gate. Consequently, the gate carries a negative charge. If the negative charge on the floating gate is above a selected threshold level, the bit stored in the cell is defined as a “zero.” On the other hand, if a low voltage is applied to the drain or BL, the number of electrons on the floating gate does not exceed the threshold level so that the state remains the same or a “one.” Thus, the default state is “one.”
The cell programmed with a “zero” may be erased by applying a high voltage to the gate and leaving the drain or bit line open or floating. Thus, the excess electrons that were trapped on the floating gate now move to the “source” of the transistor, which is typically connected to ground so that the floating gate is again neutral.
To “read” the cell, a high voltage is applied to the gate. If the transistor is turned on, its drain output is pulled low on the bit line and is defined as a “one” using negative logic. If the transistor is not on, its drain is high on the bit line, which is defined as “zero.” The cell threshold voltage for a typical un-programmed or erased single bit cell is less than about 3.1 volts, while a cell programmed with a “zero” has a threshold voltage greater than 5.0 volts. Thus, the floating gate NMOS transistor provides a high-speed non-volatile memory cell.
As the demand increases for larger and larger non-volatile high-speed memories, the typical answer has been to aggressively decrease the geometry or size of a memory chip and simply pack more and more cells in the same area. However, demand and need is increasing faster than can be accommodated by scaling or decreased geometry. Consequently, there have now been developed flash cells that can provide two data bits per cell and effectively double the amount of storage in an array. Flash memory cells that can store 2 bits do so by using 4 different precise voltages to represent the state of the 2 bits. For example, for a “1”, “1” state, the threshold voltage is typically less than 3.0 volts. For a “1”, “0” state, the threshold voltage is typically between about 3.5 volts and 3.8 volts, and for a “0”, “1” state, the threshold voltage is typically between about 4.3 volts and 4.7 volts. Finally, for a “0”, “0” state, the threshold voltage is above about 5.5 volts.
Of course, the manufacturing process for cells having floating gates that can be charged to these precise voltage settings becomes critical. Furthermore, the circuitry for providing the necessary word line, bit line and gate voltages to achieve the necessary threshold electron charges and resulting voltages is also significantly more complicated.
Another recent development that can store 2 data bits in a single memory cell uses an ONO structure. This memory cell is a transistor with an ONO dielectric programmed by channel hot electrons pumped to the “N” or silicon nitride layer of the ONO structure, which acts as the floating gate. The electron charge is trapped in the silicon nitride layer of the drain junction edge of the ONO stack when the charge is pumped to the edge of the silicon nitride gate. Since charge can be pumped and removed at both edges of the silicon nitride gate, each edge can store a data bit that can be programmed and erased. A “read” operation is carried out in a direction opposite to the direction the bit was programmed, and an erase operation occurs as a result of tunnel enhanced hot “holes” injections created by band-to-band tunneling at the drain junction edge and acceleration occurring from the lateral field.
This type ONO memory array consists of bit lines and word lines that are orthogonal to each other and consequently are presently the densest of known flash memories and at present appear to have a greater future potential than other memory types. Unfortunately, the prior art structures now available are often unreliable in the write and erase operations, because of the difficulty of properly locating the erasing charge over the charged site. Therefore, an ONO or other multilayered type dual bit memory cell that demonstrates reliable write and erase operations would be advantageous.